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General Information

The main goal of this NATO Advanced Research Workshop is to examine (at the atomic scale) the very complex scientific issues that pertain to the use of advanced high dielectric constant (high-k) materials in next generation semiconductor devices. The unique feature and novelty of this workshop is a special focus on an important issue of defects in this novel class of materials.

Field effect transistor (the "heart" of which is a thin gate dielectric, currently SiO2-based) remains the key element of logic and memory devices in a wide variety of commercial and defense-related application. These applications are at the technical core of modern society and play a critical (although often invisible) role in every day operations, such as computing, networking, sensors, telecommunication, data storage and processing, and various systems.

Conventional SiO2/Si-based MOSFET's are quickly approaching the fundamental limit of scaling; ~ 1nm oxide thickness dimensions. Scaling of transistors is required to maintain the need for increased speed and density. Below 1 nm, very large gate leakage currents degrade dielectric reliability and prevent any practical use of the conventional SiO2. The only feasible solution to the gate oxide scaling problem is to replace SiO2 with novel high-k gate dielectrics. These materials offer significantly reduced gate leakage and allow for continued device scaling. However, despite significant progress achieved in this new area of research, high-k materials are still not ready for high volume production in the gate stack.

One of the key obstacles to high-k integration into Si nano-technology are the electronic defects in high-k materials. It has been established that defects do exist in high-k dielectrics and they play an important role in device operation. However, very little is known about the nature of the defects or about possible techniques to eliminate, or at least minimize them. Defects are also important in satellite electronics because radiation effects is a serious concern for space applications. Needless to say, the search and understanding of radiation-hardened materials (including high-k) remains a priority research area. Given the absence of a feasible alternative in the near future, well-focused scientific research and aggressive development programs on high-k gate dielectrics and related devices must continue for semiconductor electronics to remain a competitive income producing force in the global market.

To progress towards overcoming the many fundamental obstacles blocking integration of high-k dielectrics into nano-semiconductor technology and to improve our basic knowledge of these emerging materials, we have formulated a workshop, the main goal of which is to develop an atomic-scale understanding of defects in high-k and their role in devices. During our planned 4-day ARW, leading researchers meet, tutor each other about both their recent results and thinking, and perhaps come to some consensus as to where research and development should be directed over the next five years. Many of the speakers are from Europe, the U.S. and Canada. Several key speakers come from former "Eastern Block" countries including researchers from leading centers in the former USSR (Moscow, Novosibirsk, and St. Petersburg). The list of researchers represents a rather diverse group of scientists and engineers who bring a broad array of backgrounds and strengths into the workshop. The group comes from academic, industrial and governmental labs, and has both experimental and theoretical researchers with backgrounds in basic and applied areas of physics, chemistry, electrical engineering, surface science, and materials science. In the problems surrounding next-generation high-k dielectrics it is necessary for theoretical quantum chemists to speak with processing engineers, and device engineers and modelers to listen to surface physicists. The problems are complex and demand a broad and integrated vision.

We have planned the meeting thematically. Following a few introductory presentations, the first day will concentrate on processing and physical and structural properties of high-k materials (HfO2, ZrO2, Al2O3, Y2O3, silicates, etc) . A thorough knowledge of bulk materials properties and interfaces is required before these complex multi-component systems can hope to be understood or optimized. The second day will be dedicated to the experimental investigation of defects in the morning and recent state-of-the-art theoretical investigations of high-k materials in the afternoon. This day will be concluded by a poster session in the evening, giving special priority to younger researchers to present and discuss their work. In the morning of the third day we will cover an important issue of electrical characterization, defects structure and effect on device performance. In the afternoon, a trip/excursion is planned. In the morning of the fourth day we will continue with theoretical discussions, focusing on electronic structure and defects. In the afternoon, the important (especially for defense electronics) issue of radiation effects will be covered. After that, a review and open discussion will be held to focus on both individual and collective plans for future research on defects in high-K dielectrics.

This workshop continues the sucessful tradition of our series of meetings in the following important areas of nano-science and technology